VeriSim

VeriSim is a client-side Verilog simulation and synthesis tool executing entirely within the browser via WebAssembly, utilizing Icarus Verilog as the underlying engine. It provides dedicated editors for design and testbench files, console output, waveform viewing, and circuit synthesis to visualize gate-level or RTL representations. Users can load source files directly from URLs or GitHub repositories, run simulations locally without backend setup, and export generated VCD files.